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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4071B gates Quadruple 2-input OR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 2-input OR gate DESCRIPTION The HEF4071B is a positive logic quadruple 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4071B gates Fig.2 Pinning diagram. HEF4071BP(N): 14-lead DIL; plastic (SOT27-1) HEF4071BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4071BT(D): 14-lead SO; plastic Fig.1 Functional diagram. (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram (one gfate). January 1995 2 Philips Semiconductors Product specification Quadruple 2-input OR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 55 25 20 45 20 15 60 30 20 60 30 20 115 50 35 90 45 30 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns 28 ns 15 ns 12 ns 18 ns 9 ns 7 ns 10 ns 9 ns 6 ns 10 ns 9 ns 6 ns + + + + + + + + + + + + SYMBOL TYP. MAX. HEF4071B gates TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1150 fi + (foCL) x VDD2 4800 fi + (foCL) x VDD 19 700 fi + (foCL) x VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 |
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